1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of forming a self-aligned silicide device.
2. Description of Related Art
As the level of integration for MOS devices is increased, resistance in the source/drain terminals of the MOS device gradually rises to a value comparable to the channel resistance of the MOS device. To ensure integrity at the shallow junction between metallic contacts and the MOS terminals, and for the downward adjustment of sheet resistance in the source/drain terminals, self-aligned silicide processes are now employed in the manufacturing of very large scale integrated (VLSI) circuits, especially for the manufacturing of semiconductor devices having a line width smaller than about 0.5 .mu.m.
When the density of integrated circuits is further increased by shrinking the device dimensions to the deep submicron level, a dual gate electrode such as an N-type/P-type gate electrode is necessary. The dual gate electrode is formed by depositing a layer of tungsten silicide (WSi.sub.X) over an ion doped polysilicon layer, and then etching the tungsten silicide layer and the polysilicon layer to form a tungsten polycide gate. However, the tungsten silicide formed using the conventional method has a high sheet resistance. Therefore, the channel length of the device is incapable of being shrunk very much. Furthermore, the doped ions in the polysilicon layer are able to cross-diffuse when subsequent thermal processes are performed.
FIGS. 1A through 1D are a series of cross-sectional views showing the progression of manufacturing steps in the production of a self-aligned silicide device according to a conventional method. First, as shown in FIG. 1A, a silicon substrate 10 is provided. Then, shallow trench isolation regions 11, a gate oxide layer 12a and a polysilicon layer 13a are sequentially formed above the substrate 10. The shallow trench isolation regions 11 are formed using an anisotropic dry etching method to form shallow trenches in the substrate 10, and then depositing silicon dioxide to fill up the trenches. The shallow trench isolation regions 11 serve to define the device active area 9. The gate oxide layer 12a can be formed, for example, by depositing a silicon dioxide layer. The polysilicon layer 13a has a thickness of about 1000-3500 .ANG., and can be formed, for example, by using a low pressure chemical vapor deposition (LPCVD) method.
Next, as shown in FIG. 1B, a tungsten silicide layer 14a is deposited over the polysilicon layer 13a. For example, tungsten hexafluoride (WF.sub.6) is used as a source gas to react chemically with silane (SiH.sub.4) or dichlo-silane (SiH.sub.2 Cl.sub.2) at a temperature of about 300.degree.-600.degree. C., and then the tungsten silicide layer 14a is deposited using a low pressure chemical vapor deposition process. Subsequently, a silicon nitride layer 15a is deposited over the tungsten silicide layer 14a. The silicon nitride layer 15a can be deposited, for example, using a low pressure chemical vapor deposition method.
Next, as shown in FIG. 1C, using conventional photolithographic and etching techniques, the gate oxide layer 12a, the polysilicon layer 13a, the tungsten silicide layer 14a and the silicon nitride layer 15a are patterned and then etched to form a gate oxide layer 12b, a polysilicon layer 13b, a tungsten silicide layer 14b, a silicon nitride layer 15b, and which exposes the remaining substrate 10 surface. The stacked polysilicon layer 13b, the tungsten silicide layer 14b and the silicon nitride layer 15b together constitute a composite gate electrode.
Finally, as shown in FIG. 1D, spacers 16 are formed around the periphery of the gate electrode, covering portions of the substrate 10. Thereafter, a titanium layer is sputtered over the spacers 16 and the exposed portions of the substrate 10. Then, rapid thermal processing is carried out to form titanium silicide layers 17 above the substrate 10 on each side of the gate electrode.
For the above conventional method, since the tungsten silicide layer 14b of the composite gate electrode layer has a high sheet resistance, the channel length of the device cannot be shrunk very much. In addition, the doped ions in the polysilicon layer of a dual gate electrode may experience heating due to subsequent thermal treatments, which may lead to a cross-diffusion of ions. Therefore, the device performance is greatly lowered.
In light of the foregoing, there is a need in the art for improving the method of forming a self-aligned silicide device.